
- Qualification
PhD, MTech( Electronic circuits & System Design), B.Sc Engg (Electronics)
- Designation
Associate Professor
- Thrust Area
VLSI
- Address
4/1109, Near Rahmat Bano Hostel, Sir Syed Nagar, Aligarh (UP)
- Mobile
9760269316
- Email
ajmal.kafeel.wp@amu.ac.in, ajmal_kafeel@hotmail.com
- Time Table
Dr M Ajmal Kafeel Completed B. Tech and M.Tech from ZH College of Engineering & Technology in the year 1998 and 2005 respectively. He has done PhD in Electronics Engg, from Deptt. Of Electronics Engineering, AMU, Aligarh . His area of research include VLSI Design of Devices , Analog and digital Circuits . He has contributed and attended various national and international conferences and published papers in reputed journals . Presently he is working as Associate Professor in Electronics Engineering at University Women's Polytechnic, AMU, Aligarh. He actively participate in university Administration and has served as an Associate Member in Charge of Department of Electricity AMU. He also served as member of University Website Committee and served as warden of University's prestigious Sir Syed Hall(North) for a period of 4 years . He is Sharing various responsibilities in the department other than teaching such as Superintendent of Examinations, scrutinizer etc.
- Publication
- "Optimization and Characterization of CMOS for Ultra Low Power Applications" Journal of Nanotechnology, 2015
- "Subthreshold Design of Second Generation Current Conveyor"Scopus Indexed International Journal of Advanced Information Science and Technology(IJAIST-IF-3.564) Volume 40, issue 40, August 2015, pages 83-92.
- “Performance Evaluation of CNFET Based Operational Amplifier at Technology node Beyond 45-nm” paper presented in the conference at IIT Bombay INDICON2013. December 13-15, 2013
- “Performance Evaluation of CNFET based Single-Ended 6T SRAM cell” SCI Indexed Wulfenia journal Volume 20, Issue 7, July 2013, pages 364-383.
- “Variability Analysis of MTJ-Based circuit” third international conference on Computer and Communication Technology (ICCCT) 2012. Pages 57-62.
- “Performance Analysis of DG FinFET for Ultralow-power Subthreshold Applications” Journal of Electronic Design Technology (STM Journals) Volume 2, Issue 2, January,2012, Pages 8-15 .
- “Robustness Comparison of Emerging Devices for Portable Applications” SCI Indexed International Journal of Nanomaterials. Volume 2012 (2012), 8 pages.
- “Variation Immune Near Threshold SRAM Cell” in proceedings of 1st International Conference on Recent Advances in Information Technology, (RAIT-2012),vol. II, pp- 286-291, (15-17th) March, 2012.
- “Low Active Power High-Speed Cache Design”, in proceedings of the IEEE International Symposium on Electronic System Design (ISED) 2011 (19-21 December 2011, Kochi, India)
- “Performance Analysis of Ultra Low-Power Mixed CNT Interconnects for Scaled Technology”, in proceedings of the IEEE International Symposium on Electronic System Design (ISED) 2011 (19-21 December 2011, Kochi, India).

